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ASAHI KASEI
[AKD4705-A]
AKD4705-A
AK4705 Evaluation Board Rev.0
GENERAL DESCRIPTION AKD4705-A is an evaluation board for quickly evaluating the AK4705, 2ch DAC with AV SCART switch. Evaluation requires audio/video analog analyzers/generators, a digital audio signal source, and a power supply. AKM's ADC evaluation board can be also used for the audio source. Also included is a AK4112B digital audio interface receiver which receives S/PDIF compatible audio data. The digital audio data is available via optical connector or BNC.
AKD4705-A --AK4705 Evaluation Board (Cable for connecting with printer port of IBM-AT compatible PC and a control software are enclosed with board. This control software dose not support Windows NT.)
FUNCTION BNC connectors for analog audio input/output BNC connectors for analog video input/output On-board clock generator BNC connector for an external clock input Compatible with 2 types of digital interface 1. Serial interface: Direct interface with evaluation boards for AKM's A/D converter evaluation boards. 2. S/PDIF: On-board AK4112BVF as DIR that accepts optical input or BNC input 10pin header for serial control interface
MO NO D5V VVD2 VVD1
JP10 Reg. PORT3 P- IF Control Data 10pin Heder Port1
AD DATA ROM DATA 10pin Header
+5V
+12V
Gnd
OU TV OU TV OU VC RO
JP11 (Digital) JP8 JP9
JP2~ 5
UT VC
RX
PORT2 Opt In
JP6
DIR
RO UT
J1 EXT JP1 Clock Generator
VC RV OU VC RC TV RC
RF
AK4705
TVI NL
TV
JP12
FB TV VO VC TV RI
TVI NR
TV ENCB ENCRC ENCV TVVIN VCRFB VCRG
VC RI VCRSB VCRB TVSB
ENCG
ENCC
ENCY
VCRVIN
VCRRC
Figure 1. AKD4705-A Block Diagram Circuit diagram and PCB layout are attached at the end of this manual.
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Operation sequence
1) Set up the power supply lines. (Note 1) [+12V] [+5V] [D5V] [VVD1] [VVD2] [AGND] [DGND] [VVSS2] (Orange) (Red) (Red) (Red) (Blue) (Black) (Black) (Black) = +11.4 +12.6V = +4.75 +5.25V (Note 2) = +4.75 +5.25V (Note 3) = +4.75 VVD2 (Note 4) = VDD1 +5.25V (Note 4) = 0V = 0V = 0V
Note: 1. Each supply line should be distributed from the power supply unit. 2. JP9 (REG) should be open when the "+5V" jack is used. 3. JP8 (D-A) should be open when the "D5V" jack is used. 4. JP10 (VDD1) / JP11 (VDD2) should be open when the "VDD1" jack / "VDD2" jack are used independently. 2) Set-up the evaluation modes, jumper pins and DIP-switches. (Refer next sections.) 3) Connect the PORT3 (P-I/F) with PC by the enclosed 10-wire flat cable. 4) Set up the PC and execute the enclosed control software. (Refer "CONTROL SOFTWARE MANUAL".) 5) Turn the power on. 6) Reset the AK4705 once by bringing the SW1 (PDN) "L", and return it to "H".
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Evaluation mode 1) S/PDIF mode (Optical Link or BNC: default)
When the CM0 (DIP-switch S1_1 on board) is "L", the AK4112B (DIR) generates MCLK, BICK, LRCK and SDATA from the received bit stream through PORT2 (TORX176: optical link) or J2 (BNC). This mode is used for the evaluation using CD test disk. The PORT1 (EXT) should be open. 1)-1. DIP-switch set-up No. 1 2 3 4 CM0 "L" "L" "L" "L" DIF2 "L" "L" "H" "H" DIF0 "L" "H" "L" "H" Audio Data Format of AK4112B 16bit LSB justified 18bit LSB justified 24bit MSB justified 24bit I2S Table 1. DIP-switch set-up
(Note) AK4112B: DIF1="L"
Notes 1 2 3 4
(Default)
Much the data format of the AK4705 via I2C-bus control as following notes. Note 1. 16bit LSB justified Set up the DIP-switch as follows.
S1 AK4112B ON OFF
(Reserved) (Reserved)
12345
Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows.
Note 2. 18bit LSB justified Set up the DIP-switch as follows.
ON OFF
CM0 DIF2 DIF0
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S1 AK4112B 12345
(Reserved)
Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows.
(Reserved)
CM0 DIF2 DIF0
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Note 3. 24bit MSB justified Set up the DIP-switch as follows.
S1 AK4112B ON OFF
(Reserved) (Reserved) (Reserved) (Reserved)
12345
Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows.
Note 4. 24bit I2S (Default) Set up the DIP-switch as follows.
ON OFF
Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows.
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CM0 DIF2 DIF0
CM0 DIF2 DIF0
S1 AK4112B 12345
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1)-2. Jumper pins set up
JP1 EXT
JP2 MCLK
JP3 BICK
JP4 SDTI
JP5 LRCK
(Open)
(Default)
(Short)
(Default)
(Short)
(Default)
(Short)
(Default)
(Short)
(Default)
The JP6 selects the input port of S/PDIF bit stream form Port2 (TOTX176) or J2 (BNC RX).
JP6
RX
JP6
RX
TORX
TORX
BNC (TORX)
(Default)
BNC (BNC)
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2) On-board X'tal mode/ Feeding external MCLK via BNC
When the CM0 (DIP-switch S1_1 on board) is "H", the AK4112B generates MCLK, BICK and LRCK from on-board X'tal or external clock form J1. SDATA should be fed via PORT1.
2)-1. DIP-switch set-up No. 1 CM0 "H" DIF1 Don't care DIF0 Don't care
Table 2. DIP-switch set-up
2)-2. Jumper pins set up
2)-2-a. Using on-board X'tal
JP1 EXT JP2 MCLK JP3 BICK JP4 SDTI JP5 LRCK
(Open) (Short) JP6: Don't care.
(Short)
(Open)
(Short)
2)-2-b. Using external clock via BNC connector J1 JP1 EXT JP2 MCLK JP3 BICK JP4 SDTI JP5 LRCK
(Short) (Short) (Short) JP6: Don't care. Remove the on-board X'tal.
(Open)
(Short)
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3) Feeding all clocks from external
Under the following set-up, all external signals can be fed to the AK4705 through POTR1 (EXT). The AKM's evaluation board for ADC can be used.
3)-1. DIP-switch set-up No. 1 CM0 Don't care DIF1 Don't care DIF0 Don't care
Table 3. DIP-switch set-up
3)-2. Jumper pins set up JP1 EXT JP2 MCLK JP3 BICK JP4 SDTI JP5 LRCK
(Open) (Open) JP6: Don't care.
(Open)
(Open)
(Open)
Other jumper pins set up
[JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4705 When the VCRC pin of the AK4705 outputs 0V by setting CIO bit to "1", the signal can be fed through the J27 (VCRCOUT) to VCRRC pin. "I": The signal is fed through the J18 (VCRRC) to VCRRC pin. (Default) "I/O": The signal is fed through the J27 (VCRCOUT) to VCRRC pin. The CIO bit of AK4705 should be set to "1".
JP12 I I/O I JP12 I/O
(I)
(Default)
(I/O)
[JP7](GND): Analog ground and digital ground Open: separated. (Default) Short: connected. (The jack "DGND" can be open.)
JP7 DGND AGND (Open)
(Default)
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DIP-switch (S1) List
No. 1 2 3 4 5 Switch Name CM0 DIF0 DIF2 Default OFF ON ON OFF OFF Function S/P DIF mode (Refer the evaluation mode) 24 bit I2S mode (Refer the evaluation mode) (Reserved) (Reserved) Table 4. DIP-switch list Jumper List No. 1 2,3, 4,5 6 Jumper Name MCLK source set-up when CM0="H". EXT MCLK, BICK, LRCK, SDTI RX
Open: X'tal (Default). Short: External clock via BNC (J1). Remove the on-board X'tal.
Function
Clock source set-up
Short: Connect the DIR (AK4112B). (Default) Open: Separate the DIR. Supply clocks via Port1.
S/PDIF's port set-up when CM0="L".
TORX: Optical connector PORT2. (Default) BNC: BNC connector J2.
Analog ground and digital ground 7 GND
Open: separated (Default). Short: connected (The connector "DGND" can be open.).
Power supply source set-up for digital section of AKD4705-A. 8 D-A
Open: from the "D5V" Jack. Short: from the regulator or the "+5V" Jack. Don't connect anything to the "D5V" Jack. (Default)
Power supply source set-up for VD of AK4705. 9 REG
Open: from the "+5V" Jack. Short: from the regulator. Don't connect anything the "+5V" Jack. (Default)
Power supply source set-up for VVD1 of AK4705. 10 VVD1
Open: from the "VVD1" Jack. Short: from the regulator or the "+5V" Jack. Don't connect anything to the "VVD1" Jack. (Default)
Power supply source set-up for VVD1 of AK4705. 11 VVD2
Open: from the "VVD2" Jack. Short: from the regulator or the "+5V" Jack. Don't connect anything to the "VVD2" Jack. (Default)
Input Selection for VCRRC 12 VCRRC
"I" side: Input to VCRRC from VCRRC jack. (Default) "I/O" side: Input to VCRC from VCRC jack. (Note: Refer CIO bit of AK4705)
Table 5. Jumper list
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[AKD4705-A]
Serial Control
The AK4705-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (P-IF) with PC by 10 wire flat cable packed with the AKD4705-A. Be careful connector direction. Flat cable should be connected 10-pin header, red line put on 10pin header 5 and 6 pin.
1 10
Connect PC
SCL SDA SDA(ACK) AKD4705-A
RED 10 wire flat cable 5 10 pin Connector PORT3 6
P-IF
10 pin Header
Figure 2. Connection of 10 pin flat cable for PORT3
Input/Output port List
Signal Name Input Audio Output Digital Input Input Video Output Slow Blanking Fast Blanking Input Output Input Output J5 (VCRINL), J3 (VCRINR), J9 (TVINL), J8 (TVINR) J12 (VCROUTL), J10 (VCROUTR), J6 (TVOUTL), J7 (TVOUTR), J4 (MONOOUT) Port2 (TORX176) or J2 BNC (RX) J13 (ENCB), J15 (ENCG), J17 (ENCRC), J19 (ENCC), J21 (ENCV), J23(ENCY), J25(TVVIN), J14(VCRVIN), J18(VCRRC; Note), J20(VCRG), J22(VCRB) J27 (VCRCOUT; Note), J29 (TVVOUT), J30 (TVRC), J31 (TVG), J32 (TVB), J33 (RFV), J34 (VCRVOUT) J24 (VCRSB) J24 (VCRSB) , J28 (TVSB) J16 (VCRFB) J26 (TVFB) Notes Max: 2Vrms Max: 3Vrm Max: D5V+0.3V Max: 1.5Vp-p Max: 3Vp-p Max: VP+0.3V Max: VP Max: VVD1+0.3V Max: VVD2
Note: Refer JP12 and CIO bit of the AK4705. Table 6. Input/Output port List
The indication content for LED
LED turns on during each output is "H". [LE1] Indicates unlock or parity error of S/PDIF. Connected to the ERF pin of DIR (AK4112B). (Normally off.) [LE2] Indicates the validity status of S/PDIF. Connected to the V pin of DIR (AK4112B). (Normally off.)
Toggle switch (SW1 on board) operation
"H": AK4705 is active. "L": AK4705 is powered down. (Note: When the power of AKD4705-A is ON at first, SW1 should be switched from "L" to "H".) -92006/08
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[AKD4705-A]
4) Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4705-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4705-A by 10-line type flat cable (packed with AKD4705-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4705 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "akd4705.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button
Explanation of each buttons
1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK4705. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to the AK4705, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4705, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 02h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4705 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4705, click [OK] button. If not, click [Cancel] button.
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4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is "akr".
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4705. The file type is the same as [SAVE]. (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button.
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5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button. The following is displayed.
(2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks".
Figure 1. Window of [F3]
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6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 2. [F4] window
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6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks")
Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
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7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed.
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Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
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MEASUREMENT RESULTS Audio
[Measurement condition] * Measurement unit : Audio Precision System two Cascade * MCLK : 256fs * BICK : 64fs : 48kHz * fs : 10Hz20kHz * BW : 18bit * Bit * Power Supply : VD=5V, VDD1=5V, VDD2=5V, VP=12V * Interface : DIR * Temperature : Room * Volume#0=Volume#1=0dB * Measurement signal line path: DAC Volume#0 Volume#1 TVOUTL/R Parameter S/(N+D) at 2Vrms Output DR S/N Input signal 1kHz, 0dBFS 1kHz, -60dBFS "0" data Measurement filter 20kLPF 22kLPF, A-weighted 22kLPF, A-weighted Results [dB] 93.3 96.8 97.0
Plots
Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output Figure 1-2. FFT (1kHz, -60dBFS input) Figure 1-3. FFT (Noise floor) Figure 1-4. FFT (Out-of band noise) Figure 1-5. THD+N vs. Input Level (fin=1kHz) Figure 1-6. THD+N vs. fin (Input Level=0dBFS) Figure 1-7. Linearity (fin=1kHz) Figure 1-8. Frequency Response (Input Level=0dBFS) Figure 1-9. Crosstalk (Input Level=0dBFS)
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Video
[Measurement condition] * Signal Generator : Sony Tectonics TG2000 * Measurement unit : Sony Tectonics VM700T * Power Supply : VD=5V, VDD1=5V, VDD2=5V, VP=12V : BNC * Interface : Room * Temperature * Measurement signal line path: ENCV TVVOUT, ENCRC TVRC Parameter S/N Measurement conditions Input = 0% flat field Filter = Uni-weighted, BW= 15kHz to 5MHz Input = 100%red(ENCRC), Measured at TVVOUT Input = Modulated Lamp Input = Modulated Lamp Results 73.1 Unit dB
Crosstalk DG DP
-58.9 0.67 0.83
dB % deg.
Plots
Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted) Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT) Figure 2-4 DG, DP (Input= Modulated Lamp)
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Plots (Audio)
AKM
+0
AK4705 DAC TVOUT S/(N+D) fs=48kHz
-20
-40
-60 d B r A -100
-80
-120
-140
-160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-1. FFT (fin=1kHz Input Level=0dBFS)
AKM
+0
AK4705 DAC TVOUT DR fs=48kHz
-20
-40
-60 d B r A -100
-80
-120
-140
-160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure-1-2. FFT (fin=1kHz Input Level=-60dBFS)
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[AKD4705-A]
AKM
+0
AK4705 DAC TVOUT S/N fs=48kHz
-20
-40
-60 d B r A -100
-80
-120
-140
-160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-3. FFT (Noise Floor)
Figure1-4. FFT (Outband Noise)
AKM
-70
AK4705 DAC THD+N vs fin fs=48kHz
-73
-76
-79
-82 d B r A -88
-85
-91
-94
-97
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-5. THD+N vs. Input level (fin=1kHz)
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[AKD4705-A]
AKM
-70
AK4705 DAC THD+N vs Input Level fs=48kHz
-73
-76
-79
-82 d B r A -88
-85
-91
-94
-97
-100 -140
-130
-120
-110
-100
-90
-80
-70 dBFS
-60
-50
-40
-30
-20
-10
+0
Figure1-6. THD+N vs. Input Frequency (Input level=0dBFS)
AKM
+0
AK4705 DAC Linerarty fs=48kHz
-12
-24
-36
-48 d B r A -72
-60
-84
-96
-108
-120 -120
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure1-7.Linearity (fin=1kHz)
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[AKD4705-A]
AKM
+1
AK4705 DAC Frequency Responce fs=48kHz
+0.8
+0.6
+0.4
+0.2 d B r A -0.2
+0
-0.4
-0.6
-0.8
-1 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-8. Frequency Response (Input level=0dBFS)
AKM
-60 -65 -70 -75 -80 -85 d B -90 -95 -100 -105 -110 -115 -120 20
AK4705 DAC Crosstalk fs=48kHz
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure1-9. Crosstalk (Input level=0dBFS)
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Plots(Video)
Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted)
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Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT)
Figure 2-4 DG, DP (Input= Modulated Lamp)
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Revision History
Date (YY/MM/DD) 05/09/27 06/08/30 Manual Board Reason Revision Revision KM078600 0 First Edition KM078601 0 Modification Contents
Comment addition
P1. Title: Evaluation board Rev.0 for AK4705 AK4705 Evaluation Board Rev.0 P3. 1)-1 DIP switch set-up: Table1 Add (Note) AK4112B: DIF1="L" Add "Default " P4. Notes 4.
Modification Comment addition
24bit I2S 24bit I2S (Default) P4. Note3, Note4: Delete the check mark of MUTE, STBY
P5-P7. JP1 (EXT), JP2 (MCLK), JP3 (BICK), JP4 (SDTI), JP5 (LRCK), JP7 (GND): Add "Short", "Open", "Default " JP6 (RX): Add "TORX", "BNC", "Default " JP12 (VCRRC): Add "I", "I/O", "Default " P8. DIP-switch (S1) List: Switch Name: DIF0, Default: OFF ON Switch Name: DIF2: Default: OFF ON P8. Jumper List: No.1: EXT Short: X'tal (default) Open: X'tal (Default) Open: External clock via BNC (J1) Short: External clock via BNC (J1) No.8: D-A Open: from the "D-5V" Jack.(default) Open: from the "D-5V" Jack.
Error Correct
No.12: VCRRC "I" side: Input to VCRRC from VCRRC jack "I" side: Input to VCRRC from VCRRC jack (Default)
P25. Figure 2-3. Y/C Crosstalk: Plot Correct
- 26 -
2006/08
ASAHI KASEI
[AKD4705-A]
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 27 -
2006/08
5
4
3
2
1
CN1
48 47 46 45 44 43 42 41 40 39 38 37
CN3 CN4
D
D
1 C16 +
2 48 45 41 39 47 43 46 44 42 40 38 37 (VVSS) 3 1 4 C23 3 5
C
C17
36
0.1u 10u
C13 (VSS) + C19 + 35 VCRVOUT PDN TVFB SDTI SCL BICK VD MCLK SDA LRCK VSS RFV
10u
PVCOM DVCOM VP 36 C12 35 34 33 32 31 30 29 28 27 26 25
VCRC VVSS TVVOUT VVD2 TVRC TVG TVB VVD1 REFI ENCB ENCG
2
0.1u
10u
C18
34
10u
0.1u
C20 +C21
33
C
C22
+
4 5 6
MONOOUT
0.1u
6 C15 + 7 R555 8 10k
U3
TVOUTL TVOUTR VCROUTL VCROUTR TVINL TVINR VCRINL
0.1u
10u
32
10u
C14
7 8 9 10 11
AK 4705
31
0.1u
30
29
9
VCRVIN
12
VCRRC
VCRSB
VCRFB
ENCRC TVVIN ENCC ENCV ENCY
VCRINR TVSB
VCRG
VCRB
10
13
14
15
16
17
18
19
20
21
22
INT
B
28
B
23
24
27
11 26 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CN2
A A
Title Size A Date:
5 4 3 2
Document Number
AKD4705-A-48LQFP AK4705
Sheet
Rev
1
1
of
1
0
5
4
3
2
1
R1 4112B_3.3V 5.1
C1 + C2
10u
C3
D
0.1u
CM0
MCLK BICK LRCK SDATA Logic
1 2 3 4 5
PORT1 10 9 8 7 6
R2 10k Logic
D
Logic
U2A 1 2 74HCU04 C5
JP1 EXT 22p
2 X1
J1 BNC R3 75
(OPEN) 1 C6
22p
(OPEN)
C
PDN R6 18k 4112B_3.3V
C7 + C8
B
Logic
L1
PORT2 6 5 6 5 GND VCC GND OUT 4 3 2 1 R-PACK5R 13
TORX176
R7 J2
A
470
C11 R8
BNC(RX)
75
0.1u
Size A Date:
5 4 3 2
+
10u
C4
0.1u
1 2 3 4 5 6 7 8 9 10 11 12 13 14
U1
EXT
12.288MHz
DVDD DVSS TVDD V/TX XTI XTO PDN R AVDD AVSS RX1 DIF0/RX2 DIF1/RX3 DIF2/RX4
CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCK01 MCK02 DAUX BICK SDTO LRCK ERF FS96 P/S AUTO
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R82 10k R83 INTRUPT
JP2 MCLK
300
R9 R12
100 100 100 100
MCLK BICK SDTI
JP3 JP4 JP5
BICK SDTI LRCK
R11 R10
LRCK Logic
U2B
R4 4
LE1
C
AK4112BVF
3
74HCU04
1k
R5 6
ERF
LE2
DIF0 DIF2 CM0 DIF0 DIF2
1 2 3 4 5
U2C S1
AK4112B
10 9 8 7 6 SW DIP-5
5
74HCU04
1k
V
Logic
U2D 9 8 74HCU04
10u
0.1u
RP1 5 4 3 2 1
CM0 DIF0 DIF2
U2E 11 10 74HCU04 U2F 12 74HCU04
B
47u
C9
C10 +
0.1u
10u
JP6 RX TORX
A
BNC
Title Document Number
AKD4705-A AK4112B
Sheet
Rev of
1
1
6
0
5
4
3
2
1
LRCK
BICK
PDN
MCLK
SDTI
RFV
SDA
SCL
VCRVOUT
+5V
CN1
TVFB
48
47
46
45
44
43
42
41
40
39
38
D
VCRC
1
37
CN3 CN4
36
D
2 (VVSS2) 35 3 34
TVVOUT
VVD2
TVRC
C
4 33 5
+12V
MONOOUT
C
32
TVOUTL
TVG
6 31
TVOUTR
TVB
7 30
VCROUTL
VVD1
ENCB
B
8 29 9 28 10 27
VCROUTR
B
ENCG
ENCRC
TVINL
11 26
ENCC
TVINR
12 13 14 15 16 17 18 19 20 21 22 23 24 25
VCRINL
CN2
VCRFB VCRRC VCRG VCRB INTRUPT VCRVIN ENCV TVVIN ENCY
A
VCRSB
JP7 GND Analog Ground
5
TVSB
Title Size A Date:
4 3 2
VCRINR
A
Digital Ground
Document Number
AKD4705-A AK4705
Sheet
Rev of
1
2
6
0
5
4
3
2
1
D
VCRINR R17 0.47u (open)
(VVSS)
MONOOUT 10k
R18
300
+
J3 VCRINR
C24
+
R15
C25
R16
J4
10u
300
MONOOUT
D
(VVSS) (VVSS)
(VVSS) J6
VCRINL R21 0.47u (open) J8 TVINR
(VVSS)
TVOUTL 10k
R22
300
+
J5 VCRINL
C26
+ (VVSS)
R19
C27
R20
10u
300
TVOUTL
(VVSS)
(VVSS) J7
From Analog output
TVINR R26 0.47u (open)
(VVSS) (VVSS)
TVOUTR 10k
R25
300
+
C
C29
+
R24
C28
R23
10u
300
TVOUTR
C
FOR Analog input
(VVSS) C31 R28
(VVSS) J10
TVINL R29 0.47u (open)
B
VCROUTL 10k
R30
300
+
J9 TVINL
C30
+ (VVSS)
R27
10u
300
VCROUTL
(VVSS)
(VVSS) C33 R32
(VVSS) J12
B
VCROUTR 10k
R34
+
10u
300
VCROUTR
(VVSS)
(VVSS)
A
A
Title Size A Date:
5 4 3
AKD4705-A
Document Number Rev
Analog Input/Output Circuit Thursday, August 17, 2006 3 6 of Sheet
2 1
0
5
4
3
2
1
R35
R36
U4 2 3 4 5 6 7 8 9 1 19 A1 A2 A3 A4 A5 A6 A7 A8 G1 G2 74HCT541 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 18 17 16 15 14 13 12 11
Logic 10k
R39
D
R37
100 SCL Logic
D1 R38
470
R40
10k
U5A 1 2 74HCT14 C34 SW1 3 U5B 4 74HCT14 PDN
D
PORT3 1 2 3 4 5 10 9 8 7 6
10k SCL SDA SDA(ACK)
R41
470
H
L
51 uP-I/F
PDN
0.1u
U5C 5 6 74HCT14 1
U6A 2 74LS07 U6B 4 74LS07 U6D 8 74LS07 U6E 10 74LS07 U6F 12 74LS07
R42 U6C 6 74LS07
U5D
3 8 9
10k
R43
Logic SDA
9
5
C
(short)
74HCT14 U5E 11 10 74HCT14 U5F 13 12 74HCT14
C
SDA(ACK)
11
13
D5V JP8 Logic D-A
B
+5V
L2
T1 NJM78M05FA
+12V R44
JP9
GND 3 OUT IN 1 C35 + C36
10u
+C39
REG
C37
+12V (short)
B
+
C38
2
0.1u
0.1u
47u
47u R45 +5V (short) VVD1 JP10 VDD1 VVD2
47u Logic
T2 LP2950A 4112B_3.3V C49 C46 GND 1 OUT IN 3 C47 + C48
C41 0.1u Logic 47u 0.1u
C42 0.1u
C43 0.1u
C44 0.1u
C45 0.1u
+ C40
47u
VVD1
A
R14 5.1
0.1u
2
47u
+
for 74HCT14, 74HCU04, 74LS07, 74HCT541
A
Title
R13 VVD2 (short)
5
JP11 VDD2
4 3
Size A Date:
Document Number
AKD4705-A POWER SUPPLY
Sheet
Rev
4
1
of
6
0
2
5
4
3
2
1
J13 ENCB
R70 (short)
R46 75
C50
J14 VCRVIN ENCB R47 75
(VVSS2) (VVSS2)
R77 (short)
C51 VCRVIN 0.1u
D
0.1u
D
(VVSS2)
J15 ENCG
(VVSS2)
R71 R48 75 (short)
C52
J16 VCRFB ENCG R49 75
(VVSS2) (VVSS2)
R78 VCRFB 300
0.1u
(VVSS2)
(VVSS2) R72
J17 ENCRC R50 75
C
C53 ENCRC 0.1u
J18 VCRRC R51 75
(VVSS2) (VVSS2)
JP12 I
R79 (short)
C54 VCRRC 0.1u VCRCOUT
C
(short)
I/O VCRRC
(VVSS2)
(VVSS2)
J19 ENCC R52 75
(VVSS2) (VVSS2)
R73 (short)
C55 ENCC 0.1u
J20 VCRG R53 75
(VVSS2) (VVSS2)
R80 (short)
C56 VCRG 0.1u
J21 ENCV
B
R74 R54 75 (short)
C57 ENCV 0.1u
J22 VCRB R55 75
(VVSS2) (VVSS2)
R81 (short)
C58 VCRB 0.1u
B
(VVSS2)
(VVSS2)
J23 ENCY R57 75
(VVSS2) (VVSS2)
R75 (short)
C59 ENCY 0.1u
J24 VCRSB R58 10K
(VVSS) (VVSS)
R56 VCRSB 300
A
J25 TVVIN R59 75
(VVSS2)
5
R76 (short)
C60 TVVIN 0.1u
Size A Date:
4 3
A
Title Document Number
AKD4705-A
Rev
(VVSS2)
Video Block Input 5 of 6 Circuit Sheet
2 1
0
5
4
3
2
1
R61
J27
75 VCRC
VCRCOUT RFV
R67
J33
300
RFV
D
VCRCOUT
R63 J29
D
(VVSS2)
(VVSS2)
75 TVVOUT
TVVOUT
R60 J26
75 TVFB
(VVSS2) R64 J30
TVFB
75 TVRC
TVRC
R62 J28
(VVSS2)
300 TVSB
TVSB
C
C
(VVSS2) R65 J31
75 TVG
TVG
(VVSS2)
(VVSS2) R66 J32
75 TVB
B
TVB
B
(VVSS2) R68 J34
75 VCRVOUT
VCRVOUT
(VVSS2)
A
A
Title Size A Date:
5 4 3
AKD4705-A
Document Number Rev
Video Block Output6 Circuit 6 of Sheet
2 1
0

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